timing > media coverage
Media Coverage
| Use an Off-The-Shelf Signal Source as a Jitter/Wander Generator EDN > February 3, 2005 Ensuring that network products meet stringent timing specifications usually requires a specialized jitter/wander generator. This Design Idea, authored by Zarlink’s Slobodan Milijevic, describes using a standard function generator equipped with PM (phase modulation) or FM (frequency modulation) to measure jitter and wander tolerance as a substitute. 
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| Timing Redundancy in Telecommunication Systems DesignFax > January 13, 2005 In a typical telecommunication product, all cards are synchronized to the same clock. The failure of this clock disrupts the data traffic on all cards. To avoid this problem and increase network reliability, telecom products are designed with active and redundant clocks. In this article, Zarlink’s Slobodan Milijevic outlines the importance of clock redundancy, presents two methods (parallel and serial) used to implement timing redundancy, and discusses the advantages and disadvantages of both approaches. Read the News |
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| Adding Timing Redundancy to Comm Equipment Designs CommsDesign > December 8, 2004 Zarlink’s Slobodan Milijevic looks at serial timing redundancy as a technique that lets designers align primary and secondary timing card clocks and, in turn, bring better timing redundancy to networking and telecom equipment designs. Read the News |
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| ZL30105: Carrier-Class Performance With Digital Timing Chips For
Networking AnalogZone > June 14,2004 In a review of Zarlink’s ZL30102 and ZL30105 digital PLLs (phase locked-loops) targeting high-growth network equipment markets, AnalogZone said, “to call these products just DPLLs would be woefully short of reality.” Read the News
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| High performance synchronization designs in transmission systems EDN Asia Special Report > May 2004 Network synchronization and clock generation is the most important part of all high-speed transport network systems. In this paper, Ullas Kumar, Applications Engineering Manager - Asia Pacific with Zarlink, describes jitter and wander, the causes of these clock impairments and how they affect the transmission system. Read the News |
| Read the News (Chinese PDF - 1.23MB) |
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| Understanding jitter issues in OC-48/OC-192 line cards EE Times > March 1, 2004 Co-authored by Zarlink’s Russ Byers and Silvana Rodrigues, this article discusses the challenges designers face in achieving accurate network timing and synchronization in complex, high-speed SONET/SDH transmission systems where jitter generation, tolerance and transfer are key considerations. Read the News |
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| Phase noise and jitter — a primer for digital designers EE Design > July 15, 2003 Whether you're designing chips or boards, understanding phase noise and jitter is crucial in high-speed design. In this tutorial, Zarlink's Neil Roberts explains what digital designers need to know. Read the news |
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